1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a self-aligned, extended metal gate using a damascene process.
2) Description of the Prior Art
As semiconductor geometries continue to shrink, and design requirements demand faster performance, gate contact resistance becomes increasingly important to reduce the circuit delay. Metal gates are an attractive option for reducing gate contact resistance, however, several problems prevent economical commercial manufacturing of metal gates.
Etching the top layer of a gate structure to expose form an opening for a metal gate layer can cause erosion of the adjacent dielectric material (eg gapfill layer or STI). This erosion of the gapfill layer can cause poly wrap around effects wherein a higher electrical field is created where a polysilicon layer fills in the gap caused by the erosion, increasing the risk of poly breakdown.
Another problem associated with forming metal gates as gate geometries continue to shrink is that patterning accuracy is reduced by performing photolithography on non-planar surfaces. Because prior art processes for forming metal gates require photolithography steps to be performed on non-planar surfaces, the necessary patterning accuracy is difficult to achieve.
Also, as gate geometries continue to shrink, it becomes difficult to land contacts on the gate structure. To compensate for this, dogbone structures that extend over field isolation structures are formed to provide increase area for landing contacts. However these dogbone structures increase contact resistance causing circuit delay.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,422,289 (Pierce) shows a planarized source and drain and gate contact structure.
U.S. Pat. No. 5,856,227 (Yu et al.) shows a polycide gate process formed by ion implant through a thin residual polysilicon layer, followed by oxidation of the thin residual polysilicon layer.
U.S. Pat. No. 5,915,183 (Gambino et al.) shows a raised source and drain contact using recessed etch of a blanket polysilicon layer.
U.S. Pat. No. 5,807,779 (Liaw) shows a process for forming self-aligned source and drain contacts and local interconnect structures.
U.S. Pat. No. 5,869,396 (Pan et al.) shows a method for forming a polycide gate contact.
U.S. Pat. No. 5,856,225 (Lee et al.) shows a process for forming an implanted channel region by removing a dummy gate to form an implant opening and forming a self-aligned gate in the opening.
U.S. Pat. No. 5,731,239 (Wong et al.) shows a method for forming sclf-aligned silicide gate electrodes.